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Description: 基于VHDL编写的SDR-SDRAM控制器的编程,目前是业界常用的RAM控制器-VHDL prepared based on the SDR-SDRAM controller programming, is now commonly used in industry RAM controller
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Size: 1013760 |
Author: wfs |
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Description: ALTERA公司DDR ram controller资料-ALTERA company DDR ram controller information
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Size: 2253824 |
Author: 盛雪飞 |
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Description: 存储器模块生成,采用16位数据总线,5位读写地址总线,异步清零!-Memory modules generated, using 16-bit data bus, 5 to read and write address bus, asynchronous Clear!
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Size: 2048 |
Author: 齐磊 |
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Description: 采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下:
1.系统主时钟为100 MHz。
2.数据为16位-数据线上连续2次00FF后数据传输开始。
3.系统内部总线宽度为8位。
4.共有4个通道(ch1、ch2、ch3、ch4),每个通道配备100 Bytes的RAM,当存满数据后停止数据采集并且相应通道的状态位产生报警信号。
5.数据分为8位串行输出,输出时钟由外部数据读取电路给出。
6.具备显示模块驱动功能。由SEL信号设置显示的通道,DISPLAY信号启动所选通道RAM中数值的显示过程。数值顺次显示一遍后显示结束,可以重新设定SEL的值选择下一个通道。模块数据线为8位,显示器件为4个8段LED。
7.数据采集模式如下:单通道采集(由SEL信号选择通道),多通道顺次采集(当前通道采满后转入下一通道),多通道并行采集(每通道依次采集一个数据)。模式由控制信号MODE选择,采集数据的总个数由NUM_COLLECT给出。
8.数据采集过程中不能读取,数据读取过程中不能采集-err
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Size: 5782528 |
Author: pengfu |
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Description: TMS320F2812读写外部RAM的C语言例程,TMS320F2812读写外部RAM的C语言例程-TMS320F2812 external RAM read and write the C language routines, TMS320F2812 external RAM read and write the C language routines
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Size: 36864 |
Author: 王磊 |
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Description: Top Level Dual Port Ram Core Project, VHDL code
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Size: 1024 |
Author: mohd |
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Description: fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
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Size: 468992 |
Author: 张菁 |
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Description: 据说是 vhdl的乒乓ram 代码 提供给大家做个参考吧 -It is said VHDL code of the ping-pong ram available to the U.S. to be a reference to it
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Size: 1024 |
Author: 白饭 |
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Description: 实现双口ram的读写功能,并含有测试文件,已经经过方针验证,很好用的-the writing and reading to the dual port ram ,good
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Size: 274432 |
Author: zhangyan |
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Description: Using Block RAM for High-Performance Read.Write Cams
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Size: 55296 |
Author: ryan |
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Description: 用SmartGen 生成一个2k*8 Dual Port RAM,并通过串口发送数据初始化RAM。然后通过串口返回到上位机的串口调试程序显示。-SmartGen generated using a 2k* 8 Dual Port RAM, and sending data through the serial port to initialize RAM. And back through the serial port to the PC serial port debugger display.
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Size: 4096 |
Author: 劳杰勇 |
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Description: RAM读写控制器,用verilog实现的简单易懂的RAMROMsram控制核-Controller RAM read and write, using verilog implementation of easy-to-understand control of nuclear RAMROMsram
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Size: 3072 |
Author: 王欢 |
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Description: 一个产生RAM的VHDL代码,使用这个程序不需要调用系统的RAM,可以对这个代码进行适当的修改,以提高RAM的速度-the VHDL programe of generate RAM
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Size: 2048 |
Author: xietianjiao |
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Description: ram的硬件描述 使用VHDL语言 注释也十分详细 想要的赶紧下载吧-ram using VHDL hardware description language is also very detailed notes quickly want to download it
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Size: 2048 |
Author: kongde |
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Description: ram的vhdl源代码在colloy实现-ram in the vhdl source code to achieve colloy
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Size: 1920000 |
Author: mamou |
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Description: DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA-DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
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Size: 676864 |
Author: 黄达 |
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Description: VHDL code for 32 byte RAM
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Size: 1024 |
Author: Davood |
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Description: Verilog hdl code for representing ram and rom "memory" using many methods
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Size: 5120 |
Author: Muftah |
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Description: VHDL Ram interface which devaloped for 256K ram -VHDL Ram interface which devaloped for 256K ram
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Size: 34816 |
Author: Yehonatan |
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Description: FIFO RAM 存储器以FIFO形式进行的读取-FIFO RAM
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Size: 331776 |
Author: SMILE |
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